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Si4313-B1
3.4. System Timing
?
Figure 7. RX Timing
The VCO will automatically calibrate at every frequency change or power-up. The PLL T0 time is to allow for bias
settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 μs. The
total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 μs. In certain applications, the PLL T0 time
and the PLL CAL may be skipped for faster turnaround time. Contact applications support if faster turnaround time
is desired.
3.5. Frequency Control
To calculate the necessary frequency register settings, use the Silicon Labs' Wireless Design Suite (WDS) or Excel
Calculator available from the product web page. These methods offer a simple, quick interface to determine the
correct settings based on the application requirement.
Add
R/W
Function/Description
Data
POR
D7
D6
D5
D4
D3
D2
D1
D0
Default
75
R/W
Frequency Band Select
sbsel
hbsel
fb[4]
fb[3]
fb[2]
fb[1]
fb[0]
35h
76
77
R/W
R/W
Nominal Carrier Fre-
quency 1
Nominal Carrier Fre-
quency 0
fc[15]
fc[7]
fc[14]
fc[6]
fc[13]
fc[5]
fc[12]
fc[4]
fc[11]
fc[3]
fc[10]
fc[2]
fc[9]
fc[1]
fc[8]
fc[0]
BBh
80h
3.5.1. Automatic State Transition for Frequency Change
If registers 79h or 7Ah are changed in RX mode, the state machine will automatically transition the chip back to
tune and change the frequency. This feature is useful to reduce the number of SPI commands required in a
Frequency Hopping System. In turn, this reduces microcontroller activity, thereby reducing current consumption.
3.5.2. Frequency Offset Adjustment
When the AFC is disabled, the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The
frequency offset adjustment and the AFC are both implemented by shifting the Synthesizer Local Oscillator
frequency. This register is a signed register; so, in order to get a negative offset, it is necessary to take the twos
22
Rev. 1.0
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